The present invention relates to a computer system and, more particularly, to a computer system adapted to implement storage control in the computer system having plural processors by disposing a buffer storage in a storage controller and to efficiently communicate data of a storage shared by the plural processors.
Heretofore, a general purpose computer system having plural processors has a buffer storage disposed in each of its processors and, for example, a global buffer storage disposed between a shared storage shared by all the processors and the buffer storage, thereby showing the shared storage as if located closer when looked from the processors.
Also, a vector computer system having plural processors for implementing vector processing is so constructed as to communicate data of the storage shared by the plural processors, for example, by implementing data communication among the plural processors by means of a shared register, as disclosed in Japanese Patent Laid-open (kokai) Publication No. 60-37,064/1985 corresponding to U.S. Pat. No. 4,488,083. The data communication by the shared register can minimize overhead for implementing the multiple task processing of a small task, which accompanies frequent data exchange using a communication path between high-speed processors.
When the shared register is employed in the manner as described hereinabove, the problem arises that software to be used requires the register itself and takes the number of registers into account, so that flexibility somewhat lacks in extension of the system architecture and so on. Further, the shared register to be employed therein requires processing for saving/recovering the register upon switching the task, thereby requiring the shared register to be managed on the software side.
Further, the data communication by means of the shared register as in the known art described hereinabove does not pay any attention to reliability of the system, so that error correcting codes (ECC) are added in order to ensure reliability. Therefore, there must be taken measures to duplicate the shared register itself, and so on. However, for instance, the problems occur that the addition of the ECC reduces the throughput for ECC processing and that the duplication of the shared register increases the volume of hardware therefor.
Further, a three-layer memory architecture in the general purpose computer system with plural processors suffers from the problem of physical quantity. That is, the global buffer storage and so on should become somewhat large so as to correspond to the memory-size of the shared storage because all data is set as the object for storage in the buffer storage.
Furthermore, the computer system having the vector processor requires the vector processor to be connected to the main storage through a path of a high data throughput in order to feed a large number of data at a high speed to the vector processor. Therefore, the essential problem exists in the system configuration that there cannot be so disposed something like an intermediate buffer storage which can make the main storage look closer. In other words, the vector processor is connected to the main storage through the connection path having a high data throughout. Thus data is frequently read from and written in the buffer storage always at such a high throughput even if something like the buffer storage would be disposed between the vector processor and the main storage. Therefore, the contents of the buffer storage are always replaced, thereby constantly causing the data transfer to occur between the buffer storage and the main storage and as a result making the buffer storage no use. In summary, even if the buffer storage would be disposed, a data access time to the buffer storage may become the same as that to the main storage or longer.
As described hereinabove, the computer system having the vector processor cannot be provided with something like the intermediate buffer storage so as to have the main storage look closer in the general purpose computer system, whereby the computer system having the vector processor should cause data accompanying no vector data, such as scalar instruction, control instruction and so on, to be always made access to the main storage when data is transferred between the plural processors.